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june 2013 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver FAN3121 / fan3122 single 9-a high-speed, low-side gate driver features ? industry-standard pin-out with enable input ? 4.5-v to 18-v operating range ? 11.4 a peak sink at v dd = 12 v ? 9.7-a sink / 7.1-a source at v out = 6 v ? inverting configuration (FAN3121) and non-inverting configuration (fan3122) ? internal resistors turn driver off if no inputs ? 23-ns / 19-ns typical rise/fall times (10 nf load) ? 20-ns typical propagation delay time ? choice of ttl or cmos input thresholds ? millerdrive? technology ? available in thermally enhanced 3x3 mm 8-lead mlp or 8-lead soic package (pb-free finish) ? rated from ?40c to +125c ? automotive qualified to aec-q100 (f 085 versions) applications ? synchronous rectifier circuits ? high-efficiency mosfet switching ? switch-mode power supplies ? dc-to-dc converters ? motor control ? automotive-qualified systems (f085 versions) description the FAN3121 and fan3122 mosfet drivers are designed to drive n-channel enhancement mosfets in low-side switching applications by providing high peak current pulses. the drivers are available with either ttl input thresholds (fan312xt) or v dd -proportional cmos input thresholds (fan312xc). internal circuitry provides an under-voltage lockout functi on by holding the output low until the supply voltage is wi thin the operating range. fan312x drivers incorporate the millerdrive? architecture for the final output stage. this bipolar / mosfet combination provi des the highest peak current during the miller plateau stage of the mosfet turn-on / turn-off process. the FAN3121 and fan3122 drivers implement an enable function on pin 3 (en), previously unused in the industry-standard pin-out. the pin is internally pulled up to v dd for active high logic and can be left open for standard operation. the commercial FAN3121/22 is available in a 3x3 mm 8-lead thermally-enhanced mlp package or an 8-lead soic package. the aec-q 100 automotive-qualified versions are available in the 8-lead soic package. 1 2 3 6 7 8 4 5 vdd gnd en in vdd out gnd out 1 2 3 6 7 8 4 5 en in vdd gnd vdd gnd out out figure 1. FAN3121 pin configuration figure 2. fan3122 pin configuration
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 2 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver ordering information part number logic input threshold package packing method quantity per reel FAN3121cmpx inverting channels + enable cmos 3x3 mm mlp-8 tape & reel 3,000 FAN3121cmx soic-8 tape & reel 2,500 FAN3121cmx_f085 (1) soic-8 tape & reel 2,500 FAN3121tmpx ttl 3x3 mm mlp-8 tape & reel 3,000 FAN3121tmx soic-8 tape & reel 2,500 FAN3121tmx_f085 (1) soic-8 tape & reel 2,500 fan3122cmpx non-inverting channels + enable cmos 3x3 mm mlp-8 tape & reel 3,000 fan3122cmx soic-8 tape & reel 2,500 fan3122cmx_f085 (1) soic-8 tape & reel 2,500 fan3122tmpx ttl 3x3 mm mlp-8 tape & reel 3,000 fan3122tmx soic-8 tape & reel 2,500 fan3122tmx_f085 (1) soic-8 tape & reel 2,500 all standard fairchild semiconductor products are rohs compli ant and many are also ?green? or going green. green means the products are rohs compliant and they have limits on addi tional substances of chlo rine, bromine and antimony. for additional information on fairchild?s ?green? eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . note: 1. qualified to aec-q100. package outlines figure 3. 3x3 mm mlp-8 (top view) figure 4. soic-8 (top view) thermal characteristics (2) package ? jl (3) ? jt (4) ? ja (5) ? jb (6) ? jt (7) units 8-lead 3x3 mm molded leadless package (mlp) 1.2 64 42 2.8 0.7 c/w 8-pin small outline integrated circuit (soic) 38 29 87 41 2.3 c/w notes: 2. estimates derived from thermal simulati on; actual values depend on the application. 3. theta_jl ( ? jl ): thermal resistance between the semiconductor j unction and the bottom surface of all the leads (including any thermal pad) that ar e typically soldered to a pcb. 4. theta_jt ( ? jt ): thermal resistance between the semiconductor junction and the top surf ace of the package, assuming it is held at a uniform te mperature by a top-side heatsink. 5. theta_ja ( ja ): thermal resistance between junction and ambi ent, dependent on the pcb design, heat sinking, and airflow. the value given is for natural convecti on with no heatsink, as specified in jedec standards jesd51-2, jesd51-5, and jesd51-7, as appropriate. 6. psi_jb ( ? jb ): thermal characterization parameter prov iding correlation between semiconductor junction temperature and an application circuit boar d reference point for the thermal environment defined in note 5. for the mlp-8 package, the board refer ence is defined as the pcb copper connected to the thermal pad and protruding from either end of the package. for the soic-8 package, t he board reference is defined as the pcb copper adjacent to pin 6. 7. psi_jt ( ? jt ): thermal characterization parameter provid ing correlation between the semiconductor junction temperature and the center of the top of the pack age for the thermal environm ent defined in note 5.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 3 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver pin definitions FAN3121 fan3122 name description 3 3 en enable input . pull pin low to inhibit driver. en has logic thresholds for both ttl and cmos in thresholds. 4, 5 4, 5 gnd ground . common ground reference for input and output circuits. 2 2 in input . 6, 7 out gate drive output . held low unless required input is present and v dd is above the uvlo threshold. 6, 7 out gate drive output (inverted from the input). held low unless required input is present and v dd is above the uvlo threshold. 1, 8 1, 8 v dd supply voltage . provides power to the ic. p1 thermal pad (mlp only) . exposed metal on the bottom of the package; may be left floating or connected to g nd; not suitable for carrying current. 1 2 3 6 7 8 4 5 vdd gnd en in vdd out gnd out 1 2 3 6 7 8 4 5 en in vdd gnd vdd gnd out out figure 5. FAN3121 pin assignments (repeated) figure 6. fan3122 pin assignments (repeated) output logic FAN3121 fan3122 en in out en in out 0 0 0 0 0 (8) 0 0 1 (8) 0 0 1 0 1 (8) 0 1 1 (8) 0 (8) 0 1 (8) 1 (8) 0 1 (8) 1 1 note: 8. default input signal if no external connection is made.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 4 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver block diagram en 3 8 v dd 6 5 gnd uvlo v dd_ok in 2 100k 100k 100k v dd inverting (FAN3121) non-inverting (fan3122) 7 v dd 1 4 gnd out (fan3122) out (FAN3121) out (fan3122) out (FAN3121) 100k figure 7. block diagram
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 5 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd v dd to gnd -0.3 20.0 v v en en to gnd gnd - 0.3 v dd + 0.3 v v in in to gnd gnd - 0.3 v dd + 0.3 v v out out to gnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperature (10 seconds) +260 c t j junction temperature -55 +150 c t stg storage temperature -65 +150 c recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dd supply voltage range 4.5 18.0 v v en enable voltage en 0 v dd v v in input voltage in 0 v dd v t a operating ambient te mperature -40 +125 oc
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 6 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver electrical characteristics unless otherwise noted, v dd =12 v and t j =-40c to +125c. currents are defi ned as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit supply v dd operating range 4.5 18.0 v i dd supply current, inputs / en not connected ttl 0.65 0.90 ma cmos (9) 0.58 0.85 v on turn-on voltage 3.5 4.0 4.3 v v off turn-off voltage 3.30 3.75 4.10 v FAN3121tmx_f085, fan3122tmx_f085 (aut omotive-qualified versions) v off turn-off voltage (13) 3.25 3.75 4.15 v inputs (ttl, fan312xt) (10) v il_t inx logic low threshold 0.8 1.0 v v ih_t inx logic high threshold 1.7 2.0 v v hys_t ttl logic hysteresis voltage 0.40 0.70 0.85 v FAN3121tmx, fan3122tmx i in+ non-inverting input current in from 0 to v dd -1 175 a i in- inverting input current in from 0 to v dd -175 1 a FAN3121tmx_f085, fan3122tmx_f085 (aut omotive-qualified versions) i inx_t non-inverting input current (13) in=0 v -1.5 1.5 a i inx_t non-inverting input current (13) in=v dd 90 120 175.0 a i inx_t inverting input current (13) in=0 v -175 -120 -90 a i inx_t inverting input current (13) in=v dd -1.5 1.5 a inputs (cmos, fan312xc) (10) v il_c inx logic low threshold 30 38 %v dd v ih_c inx logic high threshold 55 70 %v dd v hys_c cmos logic hysteresis voltage 12 17 24 %v dd FAN3121cmx, fan3122cmx i in+ non-inverting input current in from 0 to v dd -1 175 a i in- inverting input current in from 0 to v dd -175 1 a FAN3121cmx_f085, fan3122cmx_f085 (aut omotive-qualified versions) i inx_c non-inverting input current (13) in=0 v -1.5 1.5 a i inx_c non-inverting input current (13) in=v dd 90 120 175 a i inx_c inverting input current (13) in=0 v -175 -120 -90 a i inx_c inverting input current (13) in=v dd -1.5 1.5 a enable (FAN3121, fan3122) v enl enable logic low threshold en from 5 v to 0 v 1.2 1.6 2.0 v v enh enable logic high threshold en from 0 v to 5 v 1.8 2.2 2.6 v v hys_t ttl logic hysteresis voltage 0.2 0.6 0.8 v r pu enable pull-up resistance 68 100 134 k ? t d1 , t d2 propagation delay, cmos en (11) 8 17 27 ns t d1 , t d2 propagation delay, ttl en (11) 14 21 33 ns continued on the following page?
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 7 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver electrical characteristics (continued) unless otherwise noted, v dd =12 v and t j =-40c to +125c. currents are defi ned as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit FAN3121cmx_f085, fan3122cmx_f085 (aut omotive-qualified versions) t d1 , t d2 propagation delay, coms en (13) 8 17 33 ns outputs i sink out current, mid-voltage, sinking (12) out at v dd /2, c load =1.0 f, f=1 khz 9.7 a i source out current, mid-voltage, sourcing (12) out at v dd /2, c load =1.0 f, f=1 khz 7.1 a i pk_sink out current, peak, sinking (12) c load =1.0 f, f=1 khz 11.4 a i pk_source out current, peak, sourcing (12) c load =1.0 f, f=1 khz 10.6 a t rise output rise time (11) c load =10 nf 18 23 29 ns t fall output fall time (11) c load =10 nf 11 19 27 ns t d1, t d2 output propagation delay, cmos inputs (11) 0 ? 12 v in , 1 v/ns slew rate 9 18 28 ns t d1, t d2 output propagation delay, ttl inputs (11) 0 ? 5 v in , 1 v/ns slew rate 9 23 35 ns i rvs output reverse current withstand (12) 1500 ma FAN3121xmx_f085, fan3122xmx_f085 (aut omotive-qualified versions) t d1, t d2 output propagation delay, cmos inputs (13) 0 ? 12 v in , 1 v/ns slew rate 9 18 35 ns v oh high level output voltage (13) v oh = v dd C v out , i out = C 1 ma 15 35 mv v ol low level output voltage (13) i out =1 ma 10 25 mv notes: 9. lower supply current due to inactive ttl circuitry. 10. en inputs have modified ttl thres holds; refer to the enable section. 11. see timing diagrams of figure 8 and figure 9. 12. not tested in production. 13. automotive-qualified f 085 version specifications. timing diagrams figure 8. non-inverting figure 9. inverting
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 8 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherwise noted. figure 10. i dd (static) vs. supply voltage (14) figure 11. i dd (static) vs. supply voltage (14) figure 12. i dd (no-load) vs. frequency figure 13. i dd (no-load) vs. frequency figure 14. i dd (10 nf load) vs. frequency figure 15. i dd (10 nf load) vs. frequency
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 9 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherwise noted. figure 16. i dd (static) vs. temperature (14) figure 17. i dd (static) vs. temperature (14) figure 18. input thresholds vs. supply voltage figure 19. input thresholds vs. supply voltage figure 20. input thresholds % vs. supply voltage figure 21. enable thresholds vs. supply voltage
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 10 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherwise noted. figure 22. cmos input thresholds vs. temperature figure 23. ttl input thresholds vs. temperature figure 24. enable thresholds vs. temperature figure 25. uvlo thresholds vs. temperature figure 26. uvlo hysteresis vs. temperature figure 27. propagation delay vs. supply voltage
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 11 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherwise noted. figure 28. propagation delay vs. supply voltage figure 29. propagation delay vs. supply voltage figure 30. propagation delay vs. supply voltage figure 31. propagation delay vs. supply voltage figure 32. propagation delays vs. temperature figure 33. propagation delays vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 12 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherwise noted. figure 34. propagation delays vs. temperature figure 35. propagation delays vs. temperature figure 36. propagation delays vs. temperature figure 37. fall time vs. supply voltage figure 38. rise time vs. supply voltage figure 39. rise and fall time vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 13 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherwise noted. figure 40. rise / fall waveforms with 10 nf load figure 41. quasi-static source current with v dd =12v (15) figure 42. quasi-static sink current with v dd =12 v (15) figure 43. quasi-static source current with v dd =8 v (15) 470f al. el. v dd v out 1f ceramic (2) x 4.7f ceramic c load 1f i out in 1khz current probe lecroy ap015 FAN3121/22 figure 44. quasi-static sink current with v dd =8 v (15) figure 45. quasi-static i out / v out test circuit notes: 14. for any inverting inputs pulled low, non-inverting inputs pulled high , or outputs driven high; static i dd increases by the current flowing through the corre sponding pull-up/down resistor , shown in figure 7. 15. the initial spike in each current waveform is a meas urement artifact caused by the stray inductance of the current-measurement loop.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 14 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver applications information the FAN3121 and fan3122 family offers versions in either ttl or cmos input configuration. in the FAN3121t and fan3122t, the input thresholds meet industry-standard ttl-logic thresholds independent of the v dd voltage, and there is a hysteresis voltage of approximately 0.7 v. these le vels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2 v is considered logic high. the driving signal for the ttl inputs should have fast rising and falling edges with a slew rate of 6v/s or faster, so the rise time from 0 to 3.3 v should be 550 ns or less. the FAN3121 and fan3122 output can be enabled or disabled using the en pin with a very rapid response time. if en is not externally connected, an internal pull- up resistor enables the driver by default. the en pin has logic thresholds for parts with either ttl or cmos in thresholds. in the FAN3121c and fan3122c, the logic input thresholds are dependent on the v dd level and, with v dd of 12 v, the logic rising edge threshold is approximately 55% of v dd and the input falling edge threshold is approximately 38% of v dd . the cmos input configuration offers a hysteresis voltage of approximately 17% of v dd . the cmos inputs can be used with relatively slow edges (approaching dc) if good decoupling and bypass techniques are incorporated in the system des ign to prevent noise from violating the input voltage hysteresis window. this allows setting precise timing intervals by fitting an r-c circuit between the controlli ng signal and the in pin of the driver. the slow rising edge at the in pin of the driver introduces a delay between the controlling signal and the out pin of the driver. static supply current in the i dd (static) typical performance characteristics, the curves are produced with all inputs / enables floating (out is low) and indicate s the lowest static i dd current for the tested configuration. for other states, additional current flows through the 100 k ? resistors on the inputs and outputs, as shown in the block diagram (see figure 7) . in these cases, the actual static i dd current is the value obtained from the curves, plus this additional current. millerdrive? gate-drive technology fan312x gate drivers inco rporate the millerdrive? architecture shown in figur e 46. for the output stage, a combination of bipolar and mos devices provide large currents over a wide r ange of supply voltage and temperature variations. the bipolar devices carry the bulk of the current as out swings between 1/3 to 2/3 v dd and the mos devices pull t he output to the high or low rail. the purpose of the miller driv e? architecture is to speed up switching by provid ing high current during the miller plateau region when the gate-drain capacitance of the mosfet is being charged or discharged as part of the turn-on / turn-off process. for applications with zero voltage switching during the mosfet turn-on or turn-off interval, the driver supplies high peak current for fast switching, even though the miller plateau is not present. th is situation often occurs in synchronous rectifier app lications because the body diode is generally conducting before the mosfet is switched on. the output pin slew rate is determined by v dd voltage and the load on the output. it is not user adjustable, but a series resistor can be added if a slower rise or fall time at the mosfet gate is needed. figure 46. miller drive? output architecture under-voltage lockout (uvlo) the fan312x startup logic is optimized to drive ground- referenced n-channel mosfets with an under-voltage lockout (uvlo) function to ens ure that the ic starts in an orderly fashion. when v dd is rising, yet below the 4.0 v operational level, this circuit holds the output low, regardless of the status of the input pins. after the part is active, the supply voltage must drop 0.25 v before the part shuts down. this hyster esis helps prevent chatter when low v dd supply voltages have noise from the power switching. this confi guration is not suitable for driving high-side p-channel mosfets because the low output voltage of t he driver would turn the p-channel mosfet on with v dd below 4.0 v. v dd bypassing and layout considerations the FAN3121 and fan3122 are available in either 8-lead soic or mlp packages. in either package, the v dd pins 1 and 8 and the gnd pins 4 and 5 should be connected together on the pcb. in typical fan312x gate-driv er applications, high-current pulses are needed to charge and discharge the gate of a power mosfet in time intervals of 50 ns or less. a bypass capacitor with low esr and esl should be connected directly between the v dd and gnd pins to provide these large current pulses without causing unacceptable ripple on the v dd supply. to meet these requirements in a small size, a ceramic capacitor of 1 f or larger is typically used, with a dielectric material such as x7r, to limit the c hange in capacitance over the temperature and / or vo ltage application ranges.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 15 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver figure 47 shows the pulsed gate drive current path when the gate driver is suppl ying gate charge to turn the mosfet on. the current is supplied from the local bypass capacitor c byp and flows through the driver to the mosfet gate and to gr ound. to reach the high peak currents possible with the fan312x family, the resistance and inductance in the path should be minimized. the localized c byp acts to contain the high peak current pulses within this driver-mosfet circuit, preventing them from dist urbing the sensitive analog circuitry in the pwm controller. pwm v ds v dd c byp FAN3121/2 figure 47. current path for mosfet turn-on figure 48 shows the path the cu rrent takes when the gate driver turns the mosfet off. i deally, the driver shunts the current directly to the source of the mosfet in a small circuit loop. for fast turn-o ff times, the resistance and inductance in this path should be minimized. pwm v ds v dd c byp FAN3121/2 figure 48. current path for mosfet turn-off operational waveforms at power up, the FAN3121 in verting driver shown in figure 49 holds the out put low until the v dd voltage reaches the uvlo turn-on th reshold, as indicated in figure 50. this facilitates pr oper startup control of low- side n-channel mosfets. v dd out in figure 49. inverting configuration the out pulses? magnitude follows v dd magnitude with the output polarity inverted from the input until steady- state v dd is reached. v dd in+ (v dd ) in- out turn-on threshold figure 50. inverting startup waveforms at power up, the fan3122 non- inverting driver, shown in figure 51, holds t he output low until the v dd voltage reaches the uvlo turn-on th reshold, as indicated in figure 52. the out pulses magnitude follow v dd magnitude until steady-state v dd is reached. v dd out in figure 51. non-inverting driver v dd in+ in- out turn-on threshold figure 52. non-inverting startup waveforms
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 16 FAN3121 / fan3122 ? single 9-a hi gh-speed low-side gate driver thermal guidelines gate drivers used to switch mosfets and igbts at high frequencies can dissipate significant amounts of power. it is important to determine the driver power dissipation and the resulting j unction temperature in the application to ensure that t he part is operating within acceptable temperature limits. the total power dissipation in a gate driver is the sum of two components, p gate and p dynamic : p total = p gate + p dynamic (1) gate driving loss: the most significant power loss results from supplying gat e current (charge per unit time) to switch the load mosfet on and off at the switching frequency. the power dissipation that results from driving a mo sfet at a specified gate- source voltage, v gs , with gate charge, q g , at switching frequency, f sw , is determined by: p gate = q g ? v gs ? f sw (2) dynamic pre-drive / shoot-through current: a power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the ?idd (no-load) vs. frequency? graphs in typical performance characteristics to determine the current i dynamic drawn from v dd under actual operating conditions: p dynamic = i dynamic ? v dd (3) once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the fo llowing thermal equation, assuming ? jb was determined for a similar thermal design (heat sinking and air flow): t j = p total ? ? jb + t b (4) where: t j = driver junction temperature; ? jb = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and t b = board temperature in location as defined in the thermal characteristics table. in a full-bridge synchronous re ctifier application, shown in figure 53, each fan3122 drives a parallel combination of two high-cu rrent mosfets, (such as fdms8660s). the typical gate charge for each sr mosfet is 70 nc with v gs = v dd = 9v. at a switching frequency of 300 khz, the total power dissipation is: p gate = 2 ? 70 nc ? 9v ? 300 khz = 0.378 w (5) p dynamic = 2 ma ? 9 v = 18 mw (6) p total = 0.396 w (7) the soic-8 has a junction-to-board thermal characterization parameter of ? jb = 42c/w. in a system application, the localized te mperature around the device is a function of the layout and construction of the pcb along with airflow across the surfaces. to ensure reliable operation, the maximu m junction temperature of the device must be prev ented from exceeding the maximum rating of 150c; with 80% derating, t j would be limited to 120c. rearr anging equation 4 determines the board temperature required to maintain the junction temperature below 120c: t b,max = t j - p total ? ? jb (8) t b,max = 120c ? 0.396 w ? 42c/w = 104c (9) for comparison, replace the soic-8 used in the previous example with the 3x3 mm mlp package with ? jb = 2.8c/w. the 3x3 mm mlp package can operate at a pcb temperature of 118 c, while maintaining the junction temperature below 120 c. this illustrates that the physically smaller mlp package with thermal pad offers a more conductive path to remove the heat from the driver. consider tradeo ffs between reducing overall circuit size with junction temperature reduction for increased reliability.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 17 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver typical application diagrams v in v out from a2 from a1 a1 a2 b1 b2 v dd in agnd out out v dd pgnd 1 2 3 6 7 8 4 5 sr en bias v dd in agnd out out v dd pgnd 1 2 3 6 7 8 4 5 en sr en en fan3122 fan3122 figure 53. full-bridge synchronous rectification v bias v in FAN3121 pwm v out sr enable active high 1 2 3 45 6 7 8 v dd in en agnd v dd out out pgnd p1 (agnd) figure 54. hybrid synchronous rectif ication in a forward converter
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 18 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver table 1. related products part number type gate drive (16) (sink/src) input threshold logic package (18) fan3111c single 1 a +1.1 a / -0.9 a cmos single channel of dual-input/single-output sot23-5, mlp6 fan3111e single 1 a +1.1 a / -0.9 a external (17) single non-inverting channel with external reference sot23-5, mlp6 fan3100c single 2 a +2.5 a / -1.8 a cmos single channel of two-input/one-output sot23-5, mlp6 fan3100t single 2 a +2.5 a / -1.8 a ttl single channel of two-input/one-output sot23-5, mlp6 fan3180 single 2 a +2.4 a / -1.6 a ttl single non-inverting channel + 3.3 v ldo sot23-5 fan3216t dual 2 a +2.4 a / -1.6 a ttl dual inverting channels soic8 fan3217t dual 2 a +2.4 a / -1.6 a ttl dual non-inverting channels soic8 fan3226c dual 2 a +2.4 a / -1.6 a cmos dual inverting channels + dual enable soic8, mlp8 fan3226t dual 2 a +2.4 a / -1.6 a ttl dual inverting channels + dual enable soic8, mlp8 fan3227c dual 2 a +2.4 a / -1.6 a cmos dual non-inverting channels + dual enable soic8, mlp8 fan3227t dual 2 a +2.4 a / -1.6 a ttl dual n on-inverting channels + dual enable soic8, mlp8 fan3228c dual 2 a +2.4 a / -1.6 a cmos dual channels of two-input/one-output soic8, mlp8 fan3228t dual 2a +2.4 a / -1.6 a ttl dual channels of two-input/one-output soic8, mlp8 fan3229c dual 2 a +2.4 a / -1.6 a cmos dual channels of two-input/one-output soic8, mlp8 fan3229t dual 2 a +2.4 a / -1.6 a ttl dual channels of two-input/one-output soic8, mlp8 fan3268t dual 2 a +2.4 a / -1.6 a ttl 20 v non-inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 fan3278t dual 2 a +2.4 a / -1.6 a ttl 30 v non-inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 fan3223c dual 4 a +4.3 a / -2.8 a cmos dual inverting channels + dual enable soic8, mlp8 fan3213t dual 4 a +4.3 a / -2.8 a ttl dual inverting channels soic8 fan3214t dual 4 a +4.3 a / -2.8 a ttl dual non-inverting channels soic8 fan3223t dual 4 a +4.3 a / -2.8 a ttl dual inverting channels + dual enable soic8, mlp8 fan3224c dual 4 a +4.3 a / -2.8 a cmos dual non-inverting channels + dual enable soic8, mlp8 fan3224t dual 4 a +4.3 a / -2.8 a ttl dual n on-inverting channels + dual enable soic8, mlp8 fan3225c dual 4 a +4.3 a / -2.8 a cmos dual channels of two-input/one-output soic8, mlp8 fan3225t dual 4 a +4.3 a / -2.8 a ttl dual channels of two-input/one-output soic8, mlp8 FAN3121c single 9 a +9.7 a / -7.1 a cmos single inverting channel + enable soic8, mlp8 FAN3121t single 9 a +9.7 a / -7.1 a ttl single inverting channel + enable soic8, mlp8 fan3122c single 9 a +9.7 a / -7.1 a cmos single non-inverting channel + enable soic8, mlp8 fan3122t single 9 a +9.7 a / -7.1 a ttl single non-inverting channel + enable soic8, mlp8 fan3240 dual 12 a > +12.0 a ttl dual-coil relay driver, timing config. 0 soic8 fan3241 dual 12 a > +12.0 a ttl dual-coil relay driver, timing config. 1 soic8 note: 16. typical currents with out at 6 v and v dd = 12 v. 17. thresholds proportional to an exte rnally supplied reference voltage. 18. automotive-qualified f085 versions are only offered in soic8 packages.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 19 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver physical dimensions b. dimensions are in millimeters. c. dimensions and tolerances per a. conforms to jedec registration mo-229, variation veec, dated 11/2001 asme y14.5m, 1994 recommended land pattern 0.05 0.00 2x 2x 0.8 max seating plane d. filename: mkt-mlp08drev2 figure 55. 3x3 mm, 8-lead molded leadless package (mlp) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 20 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver physical dimensions (continued) 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa. b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev14 f) fairchild semiconductor. land pattern recommendation seating plane c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.40 (1.04) option a - bevel edge option b - no bevel edge 0.25 cba 0.10 figure 56. 8-lead small outline integrated circuit (soic) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FAN3121 / fan3122 ? rev. 1.0.2 21 FAN3121 / fan3122 ? single 9-a high-speed, low-side gate driver

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